1. Technical Field
The present invention relates to computer architecture.
2. Description of Related Art
During the last few years camera based driver assistance systems (DAS) have been entering the market; including lane departure warning (LDW), Automatic High-beam Control (AHC), pedestrian recognition, and forward collision warning (FCW). These driver assistance systems may use real time image processing of multiple patches detected in multiple image frames captured from a camera mounted in a vehicle.
Reduced instruction set computing is a processor design strategy based on a simplified instruction set and may provide higher performance if the simplicity enables much faster execution per instruction. A processor architecture based on this strategy is known herein as a reduced instruction set computer (RISC).
A vector processor, or array processor, is a processor that implements an instruction set containing instructions that operate on one-dimensional arrays of data called vectors. A scalar processor in comparison operates on a single datum. Most commonly used processors are scalar processors.
VLIW (Very Long Instruction Word) digital signal processing units contain several sub-processing units which operate in parallel. The VLIW contains multiple op-codes which direct the various sub-processing units, thus allowing for parallel processing since each sub-unit gets its op-code at the same time. An op-code is a portion of a machine language instruction that specifies an operation to be performed.